AD1843JS datasheet(25/64 Pages) AD

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AD1843

REV. 0

–25–

Reserved Output (Slots 4 or 20)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

res

Reserved for future expansion. Read back as “0.” Should be ignored to ensure future compatibility.

Reserved Output (Slots 5 or 21)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

res

Reserved for future expansion. Read back as “0.” Should be ignored to ensure future compatibility.

CONTROL REGISTERS

Control Register Architecture

All Control Registers are cleared to their default state when either the RESET pin or the PWRDWN pin is asserted. All conversion

related Control Registers (Addresses 1–15, 25 and 27) are cleared to defaults when the conversion resources of the AD1843 are pow-

ered down through the PDNI bit in Control Register Address 28. Control Registers which manage analog DAC gain/attenuation

(Addresses 3–10) are cleared to defaults whenever the resource they manage is powered down. Finally, the three clock generator

sample phase shift Control Registers (Addresses 18, 21 and 24) are cleared to defaults whenever their associated clock generator is

powered down. Writes to Control Registers are blocked until a clearing condition no longer exists. Writes to Control Registers are

also blocked immediately after the RESET pin or the PWRDWN pin is asserted until the AD1843’s internal clocks have settled,

which is indicated by the INIT bit in Control Register Address 0. Control Registers may always be read.

Figures 12 and 13 associate the Control Registers to the AD1843 Block Diagram.

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