AD1843JS datasheet(24/64 Pages) AD

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AD1843

SERIAL INTERFACE OUTPUT

Status Word Output (Slot 0 or 16)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

ADRV

ADLV

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

res

DA2RQ

DA1RQ

ADRV

Right ADC Channel Output Valid Flag. Set to “1” if slot 3 (or 19) contains valid right ADC capture data.

ADLV

Left ADC Channel Output Valid Flag. Set to “1” if slot 2 (or 18) contains valid left ADC capture data.

DA2RQ

DAC2 Input Request Flag. Set to “1” if DAC2 is enabled and its four word stereo input buffer is not full.

DA1RQ

DAC1 Input Request Flag. Set to “1” if DAC1 is enabled and its four word stereo input buffer is not full.

res

Reserved for future expansion. Read back as “0.” Should be ignored to ensure future compatibility.

Control Register Data Output (Slots 1 or 17)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Contents of Control Register addressed in previous frame.

ADC Left Sample Output (Slots 2 or 18)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Data format may be 8-bit unsigned linear PCM, 16-bit signed linear PCM, 8-bit

µ-Law companded, or 8-bit A-Law companded.

MSB is first. DATA7:0 are ignored in 8-bit linear or 8-bit companded modes.

ADC Right Sample Output (Slots 3 or 19)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Data format may be 8-bit unsigned linear PCM, 16-bit signed linear PCM, 8-bit

µ-Law companded, or 8-bit A-Law companded.

MSB is first. DATA7:0 are ignored in 8-bit linear or 8-bit companded modes.

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