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41594B bảng dữ liệu(PDF) 74 Page - Microchip Technology

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DS41594B-page 74
Preliminary
 2011-2012 Microchip Technology Inc.
7.10
Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 7-3 and Table 7-4 show the Reset condi-
tions of these registers.
TABLE 7-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
TABLE 7-4:
RESET CONDITION FOR SPECIAL REGISTERS(2)
STKOVF STKUNF RMCLR
RI
POR
BOR
TO
PD
Condition
00
1
1
0
x
1
1
Power-on Reset
00
1
1
0
x
0
x
Illegal, TO is set on POR
00
1
1
0
x
x
0
Illegal, PD is set on POR
00
1
1
u
0
1
1
Brown-out Reset
uu
u
u
u
u
0
u
WDT Reset
uu
u
u
u
u
0
0
WDT Wake-up from Sleep
uu
u
u
u
u
1
0
Interrupt Wake-up from Sleep
uu
0
u
u
u
u
u
MCLR Reset during normal operation
uu
0
u
u
u
1
0
MCLR Reset during Sleep
u
u
u
0
u
u
u
u
RESET Instruction Executed
1u
u
u
u
u
u
u
Stack Overflow Reset (STVREN = 1)
u1
u
u
u
u
u
u
Stack Underflow Reset (STVREN = 1)
Condition
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
MCLR Reset during normal operation
0000h
---u uuuu
uu-- 0uuu
MCLR Reset during Sleep
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
WDT Wake-up from Sleep
PC + 1
---0 0uuu
uu-- uuuu
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
Interrupt Wake-up from Sleep
PC + 1(1)
---1 0uuu
uu-- uuuu
RESET Instruction Executed
0000h
---u uuuu
uu-- u0uu
Stack Overflow Reset (STVREN = 1)
0000h
---u uuuu
1u-- uuuu
Stack Underflow Reset (STVREN = 1)
0000h
---u uuuu
u1-- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.



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