41594B datasheet(53/372 Pages) MICROCHIP

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Preliminary

DS41594B-page 53

PIC12LF1840T48A

5.2.2.3

Internal Oscillator Frequency

Adjustment

The 500 kHz internal oscillator is factory calibrated.

This internal oscillator can be adjusted in software by

writing to the OSCTUNE register (Register 5-3). Since

the HFINTOSC and MFINTOSC clock sources are

derived from the 500 kHz internal oscillator, a change

in the OSCTUNE register value will apply to both.

The default value of the OSCTUNE register is ‘0’. The

value is a 6-bit two’s complement number. A value of

1Fh will provide an adjustment to the maximum

frequency. A value of 20h will provide an adjustment to

the minimum frequency.

When the OSCTUNE register is modified, the oscillator

frequency will begin shifting to the new frequency. Code

execution continues during this shift. There is no

indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

5.2.2.4

LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1). Select 31 kHz, via

software, using the IRCF<3:0> bits of the OSCCON

Clock Switch Timing” for more information. The

LFINTOSC is also the frequency for the Power-up Timer

(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock

Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<3:0> bits of the OSCCON register = 000) as the

system clock source (SCS bits of the OSCCON

enabled:

• Configure the IRCF<3:0> bits of the OSCCON

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low-Frequency Internal Oscillator Ready bit

(LFIOFR) of the OSCSTAT register indicates when the

LFINTOSC is running and can be utilized.

5.2.2.5

Internal Oscillator Frequency

Selection

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 5-1). The Internal Oscillator Frequency

Select bits IRCF<3:0> of the OSCCON register select

the frequency output of the internal oscillators. One of

the following frequencies can be selected via software:

• 32 MHz (requires 4xPLL)

•16 MHz

•8 MHz

•4 MHz

•2 MHz

•1 MHz

• 500 kHz (default after Reset)

•250 kHz

•125 kHz

•62.5 kHz

•31.25 kHz

• 31 kHz (LFINTOSC)

The IRCF<3:0> bits of the OSCCON register allow

duplicate selections for some frequencies. These dupli-

cate choices can offer system design trade-offs. Lower

power consumption can be obtained when changing

oscillator sources for a given frequency. Faster transi-

tion times can be obtained between frequency changes

that use the same oscillator source.

Note:

Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’

and the frequency selection is set to

500 kHz. The user can modify the IRCF

bits to select a different frequency.

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