41594B datasheet(323/372 Pages) MICROCHIP

323 / 372 page

 2011-2012 Microchip Technology Inc.

Preliminary

DS41594B-page 323

PIC12LF1840T48A

31.1

DC Characteristics: PIC12LF1840T48A-I (Industrial)

PIC12LF1840T48A

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C

 TA  +85°C for industrial

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

D001

VDD

Supply Voltage

PIC12LF1840T48A

1.8

2.5

—

3.6

FOSC

 16 MHz:

FOSC

 32 MHz (NOTE 2)

D002*

VDR

RAM Data Retention Voltage(1)

PIC12LF1840T48A

1.5

—

Device in Sleep mode

VPOR*

Power-on Reset Release Voltage

—1.6

—

VPORR*

Power-on Reset Rearm Voltage

PIC12LF1840T48A

—

0.8

—

Device in Sleep mode

D003

VADFVR

Fixed Voltage Reference Voltage for

ADC, Initial Accuracy

-7

1.024V, VDD

 2.5V, 85°C (NOTE 3)

2.048V, VDD

 2.5V, 85°C

D003A

VCDAFVR

Fixed Voltage Reference Voltage for

Comparator and DAC, Initial

Accuracy

-11

1.024V, VDD

 2.5V, 85°C

2.048V, VDD

 2.5V, 85°C

D003C* TCVFVR

Temperature Coefficient, Fixed Voltage

Reference

—-114

—

ppm/

°C

D003D*

VFVR/

VIN

Line Regulation, Fixed Voltage

Reference

—

0.225

—

%/V

D004*

SVDD

VDD Rise Rate to ensure internal

Power-on Reset signal

0.05

—

V/ms See Section 7.1 “Power-on Reset

(POR)” for details.

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:

This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

PLL required for 32 MHz operation.

For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting

the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or

greater.

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