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WM8352 bảng dữ liệu(PDF) 227 Page - Wolfson Microelectronics plc |
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WM8352 bảng dữ liệu(HTML) 227 Page - Wolfson Microelectronics plc |
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227 / 336 page ![]() Production Data WM8352 w PD, February 2011, Rev 4.4 227 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0 = VRTC is not driven out on SWVRTC pin 1 = VRTC is driven out on SWVRTC pin Reset by state machine. 7 AUXADC_ENA 0 AUXADC control 0 = disabled 1 = enabled Reset by state machine. 3 DCMP4_ENA 0 Digital comparator 4 enable 0 = disabled 1 = enabled Reset by state machine. 2 DCMP3_ENA 0 Digital comparator 3 enable 0 = disabled 1 = enabled Reset by state machine. 1 DCMP2_ENA 0 Digital comparator 2 enable 0 = disabled 1 = enabled Reset by state machine. 0 DCMP1_ENA 0 Digital comparator 1 enable 0 = disabled 1 = enabled Reset by state machine. Register 0Ch Power mgmt (5) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R13 (0Dh) Power mgmt (6) 15 LS_ENA 0 Limit Switch enable 0 = disabled 1 = enabled Note: internal conditions may prevent the converter from actually switching on - see DCDC/LDO Status register for actual converter status. Reset by state machine. Default held in metal mask. 11 LDO4_ENA 0 LDO4 enable 0 = disabled 1 = enabled Note: internal conditions may prevent the converter from actually switching on - see DCDC/LDO Status register for actual converter status. Reset by state machine. Default held in metal mask. 10 LDO3_ENA 0 LDO3 enable 0 = disabled 1 = enabled Note: internal conditions may prevent the converter from actually switching on - see DCDC/LDO Status register for actual converter status. Reset by state machine. Default held in metal mask. 9 LDO2_ENA 0 LDO2 enable 0 = disabled 1 = enabled Note: internal conditions may prevent the converter from actually switching on - see DCDC/LDO Status register for actual converter status. Reset by state machine. Default held in metal mask. |
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