WM8352 datasheet(202/336 Pages) WOLFSON

202 / 336 page

WM8352

Production Data

PD, February 2011, Rev 4.4

202

24.3.4

EXTERNAL INTERRUPTS

The first-level EXT_INT interrupt comprises three second-level interrupts for USB, Wall and Battery

supply status. Each of these has a status bit in Register R31 and a mask bit in Register R37, as

defined in Table 146. These flags are triggered on the rising and falling edges of the interrupt events.

ADDRESS

BIT

LABEL

DESCRIPTION

R31 (1Fh)

Comparator

Interrupt Status

EXT_USB_FB_EINT

USB_FB changed interrupt.

(Rising and Falling Edge triggered)

Note: This bit is cleared once read.

EXT_WALL_FB_EINT

WALL_FB changed interrupt.

(Rising and Falling Edge triggered)

Note: This bit is cleared once read.

EXT_BATT_FB_EINT

BATT_FB changed interrupt.

(Rising and Falling Edge triggered)

Note: This bit is cleared once read.

R39 (27h)

Comparator

Interrupt Status

Mask

15:13

“IM_” + name of respective bit

in R31

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Each bit in R39 enables or masks the

corresponding bit in R31. The default

value for these bits is 0 (unmasked).

Table 146 External Interrupts

24.3.5

CODEC INTERRUPTS

The first-level CODEC_INT interrupt comprises four second-level interrupts for the CODEC. Each of

these has a status bit in Register R31 and a mask bit in Register R39, as defined in Table 147.

These flags are triggered on the rising and falling edges of the interrupt events.

ADDRESS

BIT

LABEL

DESCRIPTION

R31 (1Fh)

Comparator

Interrupt

Status

CODEC_JCK_DET_L_EINT

Left channel Jack detection interrupt.

(Rising and Falling Edge triggered)

Note: This bit is cleared once read.

CODEC_JCK_DET_R_EINT

Right channel Jack detection interrupt.

(Rising and Falling Edge triggered)

Note: This bit is cleared once read.

CODEC_MICSCD_EINT

Mic short-circuit detect interrupt.

(Rising and Falling Edge triggered)

Note: This bit is cleared once read.

CODEC_MICD_EINT

Mic detect interrupt.

(Rising and Falling Edge triggered)

Note: This bit is cleared once read.

R39 (27h)

Comparator

Interrupt

Status Mask

11:8

“IM_” + name of respective

bit in R31

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Each bit in R39 enables or masks the

corresponding bit in R31. The default

value for these bits is 0 (unmasked).

Table 147 CODEC Interrupts

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