WM9093ECSSLASHR datasheet(38/84 Pages) WOLFSON

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WM9093

Production Data

PD, March 2012, Rev 4.2

The sequence of signals associated with a single register write operation is illustrated in Figure 7.

Figure 7 Control Interface Register Write

The sequence of signals associated with a single register read operation is illustrated in Figure 8.

Figure 8 Control Interface Register Read

The Control Interface also supports other register operations, as listed above. The interface protocol

for these operations is summarised below. The terminology used in the following figures is detailed in

Table 18.

Note that multiple write and multiple read operations are supported using the auto-increment mode.

This feature enables the host processor to access sequential blocks of the data in the WM9093

TERMINOLOGY

DESCRIPTION

Start Condition

Repeated start

Acknowledge (SDA Low)

¯¯

Not Acknowledge (SDA High)

Stop Condition

R/W

¯¯

ReadNotWrite

0 = Write

1 = Read

[White field]

Data flow from bus master to WM9093

[Grey field]

Data flow from WM9093 to bus master

Table 18 Control Interface Terminology

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