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WM8983GEFL/V bảng dữ liệu(PDF) 27 Page - Wolfson Microelectronics plc |
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WM8983GEFL/V bảng dữ liệu(HTML) 27 Page - Wolfson Microelectronics plc |
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27 / 124 page ![]() Production Data WM8983 w PD, Rev 4.3, May 2010 27 Notes: 1. The lineout charge time, tline_midrail_on, is determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7μF capacitor. 2. It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute function has been applied to the signal beforehand. 3. The lineout discharge time, tline_midrail_off, is determined by the VMID pin discharge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance. The values above were measured using a 4.7μF capacitor. 4. The headphone charge time, thp_midrail_on, is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7μF VMID decoupling capacitor. 5. The headphone discharge time, thp_midrail_off, is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance. The values above were measured using a 4.7μF VMID decoupling capacitor. 6. The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for normal DAC operation. RECOMMENDED L/ROUT1 ENABLE SEQUENCE In order to minimise click noise, it is recommended that the WM8983 headphone outputs are enabled using the following sequence: • Activate dual enable function DELEN = 1 (R42). • Enable L/ROUT1 amplifier core, LOUT1EN = 1, ROUT1EN = 1 (R2). • Enable output FETs, OUT1DEL = 1 (R42). • Disable DELEN = 0. • Reset OUT1DEL = 0. Notes: All outputs on WM8983 can also be enabled with a single write to enable bits in registers 2 and 3 without click minimisation. Disabling outputs does not require click minimisation. |
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