ST10F272M_12 datasheet(45/176 Pages) STMICROELECTRONICS

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ST10F272M

Central processing unit (CPU)

Doc ID 12968 Rev 3

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Central processing unit (CPU)

The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated

SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator

and a barrel shifter.

Most of the ST10F272M’s instructions can be executed in one instruction cycle which requires 50 ns at

40 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle

independent of the number of bits to be shifted.

Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16-bit

multiplication in 5 cycles and a 32-/16-bit division in 10 cycles.

The jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to

1 cycle.

The CPU uses a bank of 16 word registers to run the current context. This bank of general purpose

registers (GPR) is physically stored within the on-chip internal RAM (IRAM) area. A context pointer (CP)

The number of register banks is only restricted by the available internal RAM space. For easy parameter

passing, a register bank may overlap others.

A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is

allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register.

Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon

each stack access for the detection of a stack overflow or underflow.

Figure 7.

CPU block diagram (MAC unit not included)

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