STPMC1 datasheet(22/77 Pages) STMICROELECTRONICS

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Theory of operation

STPMC1

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Doc ID 15728 Rev 6

source for the linear regulator. Also, this module produces several bias currents and

voltages for all other analog modules and for the OTP module.

9.3

Resetting the STPMC1 (status bit

HLT)

The STPMC1 has no reset pin. The device is automatically reset by the power-on-reset

detection circuit (POR) when the VCC crosses the 2.5 V value, but it can be reset also

through the SPI interface through a dedicated remote reset request (RRR) command (see

paragraph

9.21 for RRR details).

The reset through SPI is used during production testing or in an application with some on-

board microprocessors when a malfunction of the device is detected.

Resetting the STPMC1 causes all the functional modules of STPMC1 to be cleared,

including the OTP shadow latches (see paragraph

9.19 for an OTP shadow latch memory

description). In case of reset through SPI the mode signals (see paragraph

9.20 for a

description of the mode signals) are not cleared.

In cases of reset caused by the POR circuit all blocks of the digital part, except the SPI

interface, are held in a reset state for 125 ms after the reset condition. When the reset is

performed through SPI, no delayed turn-on is generated.

During the device reset, the status bit

HLT is held high, meaning that data read from the

device register are not valid.

9.4

Clock generator (bits MDIV, FR1, HSA)

All the internal timing of the STPMC1 is based on the XTAL1 signal. This signal can be

generated in two different ways:

●

Quartz: the oscillator works with an external crystal.

●

External clock: the clock is provided by an external source connected to XTAL1.

The suggested circuits are depicted in

Figure 8.

Connections of oscillator: (a) quartz, (b) external source

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