CXD3003 datasheet(8/137 Pages) SONY

8 / 137 page

– 8 –

CXD3003R

∗ In the CXD3003R, the following pins are NC.

Pins 1, 2, 19, 35, 36, 37, 38, 54, 71, 72, 73, 74, 90, 107, 108, 109, 110, 127, 143 and 144

Notes) • The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's

complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the

EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

• C2PO represents the data error status.

• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.

123

124

125

126

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

1, 0

1, Z, 0

Tracking drive output.

Focus drive output.

Digital power supply.

Analog EFM PLL oscillation circuit output.

Analog EFM PLL oscillation circuit input. flock = 8.6436MHz

Test pin. Normally fixed to low.

Analog EFM PLL charge pump output.

Variable pitch clock input from the external VCO. fcenter = 16.9344MHz

Set VCKI to low when the external clock is not input to this pin.

Wide-band EFM PLL VCO2 oscillation output.

Analog power supply.

Connects the operational amplifier current source reference resistance connection.

Analog GND.

Operational amplifier output.

RF signal input.

Center servo analog input.

Tracking error signal input.

TRDR

FFDR

FRDR

DVDD5

VCOO

VCOI

TEST

TES2

TES3

PDO

VCKI

V16M

AVDD2

IGEN

AVSS2

ADIO

RFDC

No.

Symbol

I/O

Description

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