CXD3003 datasheet(37/137 Pages) SONY

37 / 137 page

– 37 –

CXD3003R

Command bit

Processing

VCOSEL1 = 0

VCOSEL1 = 1

Multiplier PLL VCO1 is set to normal speed.

Multiplier PLL VCO1 is set to approximately twice the normal speed.

Command bit

KSL3

KSL2

Processing

Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/1 frequency-divided.

Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/2 frequency-divided.

Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/4 frequency-divided.

Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/8 frequency-divided.

∗ This setting is valid only when the low-speed VCO is selected by VCO1 CS1 and CS0.

See the previous page.

Command

Data 2

MODE

specification

VCO

SEL1

ASHS SOCT

VCO

SEL2

D19

D18

D17

D16

Data 3

KSL3

KSL2

KSL1

KSL0

D15

D14

D13

D12

Command bit

Processing

VCOSEL2 = 0

VCOSEL2 = 1

Wide-band PLL VCO2 is set to normal speed.

Wide-band PLL VCO2 is set to approximately twice the normal speed.

Command bit

KSL1

KSL0

Processing

Output of wide-band PLL VCO2 selected by VCO2 CS is 1/1 frequency-divided.

Output of wide-band PLL VCO2 selected by VCO2 CS is 1/2 frequency-divided.

Output of wide-band PLL VCO2 selected by VCO2 CS is 1/4 frequency-divided.

Output of wide-band PLL VCO2 selected by VCO2 CS is 1/8 frequency-divided.

∗ This setting is valid only when the low-speed VCO is selected by VCO2 CS.

CXD3003 bảng dữ liệu(PDF) 37 Page - Sony Corporation

CXD3003 bảng dữ liệu(HTML) 37 Page - Sony Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL