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TNETX3100PGC bảng dữ liệu(PDF) 65 Page - Texas Instruments

tên linh kiện TNETX3100PGC
Giải thích chi tiết về linh kiện  ThunderSWITCHE 10-PORT 10-/100-MBIT/S ETHERNETE SWITCH
PDF  80 Pages
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nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
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TNETX3100PGC bảng dữ liệu(HTML) 65 Page - Texas Instruments

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TNETX3100
ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH
SPWS031D – JUNE 1997 – REVISED OCTOBER 1997
65
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
timing requirements (see Figure 17)
DRAM burst write cycle (TNETX3100 frame buffer write)
NO.
MIN
NOM
MAX
UNIT
1
tc(OSCIN)
Cycle time, OSCIN clock
20
ns
2
tw(OSCINH)
Pulse duration, OSCIN high
8
ns
3
tw(OSCINL)
Pulse duration, OSCIN low
8
ns
Frequency drift, OSCIN clock
±50
ppm
operating characteristics over recommended operating conditions (see Figure 17)
DRAM burst write cycle (TNETX3100 frame buffer write) (with DREF clock)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
4
tc(DREF)
Cycle time, DREF clock
20
ns
5
td(DA)†
Delay time, from DREF
↑ to DA7–DA0 valid/invalid
0
ns
5
td(DX)†
Delay time, from DREF
↑ to DX2–DX0 valid/invalid
0
ns
6
td(DRAS)†
Delay time, from DREF
↑ to DRAS transition
0
ns
7
td(DD)†
Delay time, from DREF
↑ to DD35–DD0 valid/invalid
0
ns
8
td(DOE)†
Delay time, from DREF
↑ to DOE transition
0
ns
9
td(DWE)†
Delay time, from DREF
↑ to DWE transition
0
ns
10
td(DCAS)†
Delay time, from DREF
↑ to DCAS transition
0
ns
† All DRAM terminals are specified to have less than a 7-ns variance at any temperature and voltage.
operating characteristics over recommended operating conditions (see Figure 17)
DRAM burst write cycle (TNETX3100 frame buffer write) (with OSCIN clock)
NO.
PARAMETER
MIN
MAX
UNIT
11
td(DA)
Delay time, from OSCIN
↑ to DA7–DA0 valid/invalid
3
18
ns
11
td(DX)
Delay time, from OSCIN
↑ to DX2–DX0 valid/invalid
3
18
ns
12
td(DRAS)
Delay time, from OSCIN
↑ to DRAS transition
3
16
ns
13
td(DD)
Delay time, from OSCIN
↑ to DD35–DD0 valid/invalid
3
18
ns
14
td(DOE)
Delay time, from OSCIN
↑ to DOE transition
3
18
ns
15
td(DWE)
Delay time, from OSCIN
↑ to DWE transition
3
16
ns
16
td(DCAS)
Delay time, from OSCIN
↑ to DCAS transition
3
15
ns



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