TNETX3100PGC datasheet(24/80 Pages) TI1

24 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DIO interface (continued)

Data can be read or written to the address registers using the data lines SDATA7–SDATA0 under the control

of chip select (SCS), read not write (SRNW) and ready (SRDY) signals. The physical interface is shown in

Figure 9. The DIO interface timing is shown in Figure 19 and Figure 20. (See

DIO register description.)

SAD(1–0)

SDATA(7–0)

SCS

SRNW

SRDY

TNETX3100

Host

Figure 9. DIO Interface Signals

remote hardware reset

A hardware reset can be initiated by the DIO interface, permitting remote recovery of the TNETX3100 without

requiring external glue logic to decode a DIO address and toggle the external reset signal of the TNETX3100.

A hard DIO reset is initiated by writing to address 0x4000. This address is directly decoded by the TNETX3100

and forces a hardware reset.

TNETX3100 condensed DIO memory map

Table 5 shows the DIO memory map. Each section is expanded in detail.

Table 5. TNETX3100 Condensed DIO Memory Map

DIO ADDRESS (BITS 15–0)

SHOWN IN HEX FORMAT

DESCRIPTION

AREA OF TNETX3100

0000–007F

Network address registers 16–31†

Network

0080–0093

Port 00–09 control and status registers†

Configuration

0094–009F

Reserved†

Reserved

00A0

Revision register†

Configuration

00A1

SIO/SCTRL register†

Configuration

00A2

Reserved†

Reserved

00A3

Device code†

Configuration

00A4–00B7

Port 00–09 transmit queue length†

Configuration

00B8–00CB

Port 00–09 VLAN registers†

Configuration

00CC–00CE

Free queue-length register†

Configuration

00CF

Reserved†

Configuration

00D0

FEACFG register†

Configuration

00D1

LED register†

Configuration

00D2

RAM size register†

Configuration

00D3

System-control register†

Configuration

00D4–00D7

DRAM data

Internal test

00D8

DRAM flag

Internal test

00D9–00DB

DRAM address

Reserved

† These registers are automatically loaded from the EEPROM.

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