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TLV4113MDGQREP bảng dữ liệu(PDF) 15 Page - Texas Instruments |
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TLV4113MDGQREP bảng dữ liệu(HTML) 15 Page - Texas Instruments |
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15 / 25 page ![]() 68 mils × 70 mils) with 5 vias (Via diameter = 13 mils Thermal Pad Area Single or Dual M0032−01 TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP www.ti.com............................................................................................................................................................... SGLS314D – JUNE 2006 – REVISED MAY 2008 Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. 1. Prepare the PCB with a top-side etch pattern, as shown in Figure 31. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLV411x IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLV411x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the TLV411x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. Figure 31. PowerPAD PCB Etch and Via Pattern Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP |
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