L6472 datasheet(31/69 Pages) STMICROELECTRONICS

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L6472

Functional description

Doc ID 022729 Rev 1

31/69

6.16

Internal voltage regulator

The L6472 integrates a voltage regulator which generates a 3 V voltage starting from motor

power supply (VSA and VSB). In order to make the voltage regulator stable, at least 22 µF

should be connected between the VREG pin and ground (the suggested value is 47 µF).

The internal voltage regulator can be used to supply the VDD pin in order to make the

device digital output range 3.3 V compatible (Figure 14). A digital output range 5 V

compatible can be obtained connecting the VDD pin to an external 5 V voltage source. In

both cases, a 10 µF capacitance should be connected to the VDD pin in order to obtain a

correct operation.

The internal voltage regulator is able to supply a current up to IREG,MAX, internal logic

consumption included (I

logic). When the device is in standby mode the maximum current that

can be supplied is I

REG

, STBY, internal consumption included (Ilogic, STBY).

If an external 3.3 V regulated voltage is available, it can be applied to the VREG pin in order

to supply all the internal logic and avoid power dissipation of the internal 3 V voltage

regulator (Figure 14). The external voltage regulator should never sink current from the

VREG pin.

Figure 14.

Internal 3 V linear regulator

6.17

BUSY\SYNC pin

This pin is an open drain output which can be used as the busy flag or synchronization

signal according to the SYNC_EN bit value (STEP_MODE register).

6.17.1

BUSY operation mode

The pin works as busy signal when the SYNC_EN bit is set low (default condition). In this

mode the output is forced low while a constant speed, absolute positioning or motion

command is under execution. The BUSY pin is released when the command has been

executed (target speed or target position reached). The STATUS register includes a BUSY

flag that is the BUSY pin mirror (see Section 9.1.19).

In the case of daisy chain configuration, BUSY pins of different ICs can be hard-wired to

save host controller GPIOs.

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