MMA8653FC datasheet(42/56 Pages) FREESCALE

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MMA8653FC

Sensors

Freescale Semiconductor, Inc.

6.8.2

0x2B: CTRL_REG2, System Control 2 Register

This register is used enable Self-Test, Software Reset, and Auto-Sleep. In addition, it enables you to configure the SLEEP and

WAKE mode power scheme selection.

Figure 39. 0x2B: CTRL_REG2, System Control 2 Register (Read/Write)

When the reset bit is enabled, all registers are rest and are loaded with default values. Writing ‘1’ to the RST bit immediately

resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP, or STANDBY mode.

The I2C communication system is reset to avoid accidental corrupted data access.

At the end of the boot process the RST bit is de-asserted to 0. Reading this bit will return a value of zero.

The (S)MODS[1:0] bits select which Oversampling mode is to be used shown in Table 37, “MODS Oversampling Modes". The

Oversampling modes are available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0].

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RST

—

SMODS1

SMODS0

SLPE

MODS1

MODS0

Table 36. CTRL_REG2 register

Field

Description

Self-Test Enable. Default value: 0.

ST bit activates the self-test function. When ST is set, X, Y, and Z outputs will shift. RST bit is used to activate the software

reset. The reset mechanism can be enabled in STANDBY and ACTIVE mode.

0: Self-Test disabled

1: Self-Test enabled

RST

Software Reset. Default value: 0.

0: Device reset disabled

1: Device reset enabled.

SMODS[1:0]

SLEEP mode power scheme selection. Default value: 00.

See Table 37, “MODS Oversampling Modes" and Table 38, “MODS Oversampling Modes Current Consumption and

Averaging Values at each ODR"

SLPE

Auto-SLEEP enable. Default value: 0.

0: Auto-SLEEP is not enabled;

1: Auto-SLEEP is enabled.

MODS[1:0]

WAKE mode power scheme selection. Default value: 00.

See Table 37, “MODS Oversampling Modes" and Table 38, “MODS Oversampling Modes Current Consumption and

Averaging Values at each ODR"

Table 37. MODS Oversampling Modes

(S)MODS1

(S)MODS0

Power Mode

Normal

Low Noise Low Power

High Resolution

Low Power

Table 38. MODS Oversampling Modes Current Consumption and Averaging Values at each ODR

ODR

Mode

Normal (00)

Low Noise Low Power (01)

High Resolution (10)

Low Power (11)

Current

μA OS Ratio

Current

μA

OS Ratio

Current

μA OS Ratio Current μA OS Ratio

1.56 Hz

TBD

128

TBD

1024

TBD

6.25 Hz

TBD

256

TBD

12.5 Hz

TBD

128

TBD

50 Hz

TBD

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