MCIMX503CVM8B datasheet(72/134 Pages) FREESCALE

72 / 134 page

i.MX50 Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Electrical Characteristics

NOTE

The timing parameter DDR20(tDQSCK) is not strictly required by this

DRAM MC design.

4.9

External Peripheral Interfaces

The following sections provide information on external peripheral interfaces.

4.9.1

AUDMUX Timing Parameters

The AUDMUX provides programmable interconnect logic for voice, audio and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is hence governed by the SSI module.

4.9.2

CSPI and eCSPI Timing Parameters

This section describes the timing parameters of the CSPI and eCSPI modules. The CSPI and eCSPI have

separate timing parameters for master and slave modes. The nomenclature used with the CSPI/eCSPI

modules and the respective routing of these signals is shown in Table 48.

DDR21

DQS to DQ input skew

tDQSQ

—

0.65

DDR22

DQS to DQ input hold time

tQH

0.45 tCK

-0.85

—ns

Table 48. CSPI Nomenclature and Routing

Module

I/O Access

eCSPI1

GPIO, KPP, DISP0_DAT, CSI0_DAT, and EIM_D through IOMUX

eCSPI2

DISP0_DAT, CSI0_DAT, and EIM through IOMUX

CSPI

DISP0_DAT, EIM_A/D, SD1, and SD2 through IOMUX

Table 47. DDR2 Input AC Timing

Description

Symbol

Min

Max

Unit

MCIMX503CVM8B bảng dữ liệu(PDF) 72 Page - Freescale Semiconductor, Inc

MCIMX503CVM8B bảng dữ liệu(HTML) 72 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL