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MPC8377E bảng dữ liệu(PDF) 9 Page - Freescale Semiconductor, Inc |
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MPC8377E bảng dữ liệu(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 127 page ![]() MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8 Freescale Semiconductor 9 This figure shows the undershoot and overshoot voltages at the interfaces of the device. Figure 2. Overshoot/Undershoot Voltage for GVDD/LVDD/OVDD/LBVDD SerDes up to 667 MHz L[1,2]_ nVDD 1.0 ± 50 mV V 1, 3 800 MHz 1.05 V ± 50 mV V 1, 3 Operating temperature range commerical Ta Tj Ta=0 (min)— Tj=125 (max) °C— extended temperature Ta Tj Ta=–40 (min)— Tj=125 (max) °C— Notes: 1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative direction. 2. AVDD is the input to the filter discussed in Section 25.1, “PLL Power Supply Filtering,” and is not necessarily the voltage at the AVDD pin. 3. L[1,2]_ nVDD, SDAVDD_0, XCOREVDD, and XPADVDD power inputs. Table 3. Recommended Operating Conditions (continued) Characteristic Symbol Recommended Value Unit Note GND GND – 0.3 V GND – 0.7 V Not to Exceed 10% G/L/O/LBVDD + 20% G/L/O/LBVDD G/L/O/LBVDD + 5% of tinterface1 1. Note that tinterface refers to the clock period associated with the bus clock interface. VIH VIL Note: 2. Note that with the PCI overshoot allowed (as specified above), the device does not fully comply with the maximum AC ratings and device protection guideline outlined in the PCI Rev. 2.3 Specification (Section 4.2.2.3). |
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