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DM9621 bảng dữ liệu(PDF) 25 Page - Davicom Semiconductor, Inc. |
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DM9621 bảng dữ liệu(HTML) 25 Page - Davicom Semiconductor, Inc. |
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25 / 66 page ![]() DM9621 USB2.0 to Fast Ethernet Controller Preliminary 25 Version: DM9621 -14-DS-P02 February 23, 2011 4.33 USB Packet Error Counter (82H) Bit Name Default Description 7-0 USB_ERR PHS0,RW/C USB Data Error Count This counter is increased when there has been data CRC error in USB packet. This counter can be cleared by read if register 5 is “0” or by write to this register with any data. 4.34 Ethernet Receive Packet CRC Error Counter (83H) Bit Name Default Description 7-0 RX_ERR PHS0,RW/C Ethernet RX Packet CRC Error Count This counter is increased when there has been CRC error in Ethernet receive packet. This counter can be cleared by read if register 5 is “0” or by write to this register with any data. 4.35 Ethernet Transmit Excessive Collision Counter (84H) Bit Name Default Description 7-0 ECOL_CTR PHS0,RW/C Ethernet TX Packet Excessive Collision Count This counter is increased when there has been excessive collision, i.e. continued 16 collisions, in Ethernet transmit packet. This counter can be cleared by read if register 5 is “0” or by write to this register with any data. 4.36 Ethernet Transmit Collision Counter (85H) Bit Name Default Description 7-0 COL_CTR PHS0,RW/C Ethernet TX Packet Collision Count This counter is increased when there has been collision in Ethernet transmit packet. This counter can be cleared by read if register 5 is “0” or by write to this register with any data. 4.37 Ethernet Transmit Late Collision Counter (86H) Bit Name Default Description 7-0 LCOL_CTR PHS0,RW/C Ethernet TX Packet Late Collision Count This counter is increased when there has been late collision in Ethernet transmit packet. This counter can be cleared by read if register 5 is “0” or by write to this register with any data. 4.38 RX Header Control/Status Register (91H) Bit Name Default Description 7 MODE9620 PT0,RW RX header mode 0: DM9601 compatiable, 3-byte RX header : RX_status, byte_ctr_low, byte_ctr_high 1: DM9621 mode, 4-byte RX header : RX _flag, RX_status, byte_ctr_low, byte_ctr_high 6~1 RESERVED P,RO Reserved 1 RESERVED P0,RW Reserved 0 RESERVED P0,RW Reserved |
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