DM9621 datasheet(24/66 Pages) DAVICOM

24 / 66 page

DM9621

USB2.0 to Fast Ethernet Controller

Preliminary

Version: DM9621 -14-DS-P02

February 23, 2011

4.28 General Purpose Control Register 3 (36H)

Bit

Name

Default

Description

7~0

GPC3

HP0,RW

General Purpose Control 3

Define the input mode (“0”,) or output mode (“1”) of pins GP_GRP3.

Where the GP_GRP3 are pins GPIO3 listed in pin description

4.29 General Purpose Register 3 (37H)

Bit

Name

Default

Description

7~0

GPD3

HP0,RW

General Purpose Register 3 Data

When the correspondent bit of General Purpose Control Register 3 is set, i.e.

output mode, the value of the bit is reflected to pin GP_GRP3

When the correspondent bit of General Purpose Control Register 3 is 0, i.e. input

mode, the value of the bit to be read is reflected from correspondent pins

GP_GRP3

4.30 EEPROM and PHY Control Register (3AH)

Bit

Name

Default

Description

FORCE_46

PT0,RW

Force EEPROM to 93C46 type

DET_46

P0,RO

Auto-detect EEPROM as 93C46

DET_56

P0,RO

Auto-detect EEPROM as 93C56/66

4~3

EECK_SPD

P0,RW

Re-define EEPROM EECK speed

00=0.2Mhz, 01=0.5MHz, 10=1MHz, 11=2MHz

NO_PRE

P0,RW

Do no generate Ethernet PHY preamble in MDIO

1~0

MDC_SPD

P0,RW

Re-define Ethernet PHY MDC speed

00=1Mhz, 01=3.1MHz, 10=12.5MHz, 11=0.25MHz

4.31 Pause Packet Control/Status Register (3DH)

Bit

Name

Default

Description

7~4

PAUSE_CTR

P0,RO

Pause Packet Counter

The Pause packet counter before RX SRAM flow control low threshold

reached.

3~0

PAUSE_MAX

PHS4,RW Max. Pause Packet Count

The maximum pause packet with timer FFFFH is transmit, when the RX

SRAM is still in high threshold when pause timer timeout.

4.32 Transmit Packet Counter (81H)

Bit

Name

Default

Description

7-0

TX_CTR

PS0,RO

TX Packet Count

The TX packet count in TX SRAM.

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