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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CC1021 bảng dữ liệu(PDF) 82 Page - Texas Instruments |
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CC1021 bảng dữ liệu(HTML) 82 Page - Texas Instruments |
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82 / 94 page  CC1021 SWRS045C Page 82 of 87 TEST6 Register (26h, for test only) REGISTER NAME Default value Active Description TEST6[7:4] - 0 - Reserved, write 0 TEST6[3] VGA_OVERRIDE 0 - Override VGA settings TEST6[2] AC1O 0 - Override value to first AC coupler in VGA 0: Approx. 0 dB gain 1: Approx. −12 dB gain TEST6[1:0] AC2O[1:0] 0 - Override value to second AC coupler in VGA 0: Approx. 0 dB gain 1: Approx. −3 dB gain 2: Approx. −12 dB gain 3: Approx. −15 dB gain TEST7 Register (27h, for test only) REGISTER NAME Default value Active Description TEST7[7:6] - 0 - Reserved, write 0 TEST7[5:4] VGA1O[1:0] 0 - Override value to VGA stage 1 TEST7[3:2] VGA2O[1:0] 0 - Override value to VGA stage 2 TEST7[1:0] VGA3O[1:0] 0 - Override value to VGA stage 3 STATUS Register (40h, read only) REGISTER NAME Default value Active Description STATUS[7] CAL_COMPLETE - H Set to 0 when PLL calibration starts, and set to 1 when calibration has finished STATUS[6] SEQ_ERROR - H Set to 1 when PLL failed to lock during automatic power- up sequencing STATUS[5] LOCK_INSTANT - H Instantaneous PLL lock indicator STATUS[4] LOCK_CONTINUOUS - H PLL lock indicator, as defined by LOCK_ACCURACY. Set to 1 when PLL is in lock STATUS[3] CARRIER_SENSE - H Carrier sense when RSSI is above CS_LEVEL STATUS[2] LOCK - H Logical level on LOCK pin STATUS[1] DCLK - H Logical level on DCLK pin STATUS[0] DIO - H Logical level on DIO pin RESET_DONE Register (41h, read only) REGISTER NAME Default value Active Description RESET_DONE[7] ADC_RESET_DONE - H Reset of ADC control logic done RESET_DONE[6] AGC_RESET_DONE - H Reset of AGC (VGA control) logic done RESET_DONE[5] GAUSS_RESET_DONE - H Reset of Gaussian data filter done RESET_DONE[4] AFC_RESET_DONE - H Reset of AFC / FSK decision level logic done RESET_DONE[3] BITSYNC_RESET_DONE - H Reset of modulator, bit synchronization logic and PN9 PRBS generator done RESET_DONE[2] SYNTH_RESET_DONE - H Reset digital part of frequency synthesizer done RESET_DONE[1] SEQ_RESET_DONE - H Reset of power-up sequencing logic done RESET_DONE[0] CAL_LOCK_RESET_DONE - H Reset of calibration logic and lock detector done RSSI Register (42h, read only) REGISTER NAME Default value Active Description RSSI[7] - - - Not in use, will read 0 RSSI[6:0] RSSI[6:0] - - Received signal strength indicator. The relative power is given by RSSI x 1.5 dB in a logarithmic scale. The VGA gain set by VGA_SETTING must be taken into account. See page 33 for more details. |
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