HT66F30 datasheet(92/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.60

October 24, 2011

· TMnAH Register

Bit

76543210

Name

¾¾¾¾¾¾

R/W

¾¾¾¾¾¾

R/W

POR

¾¾¾¾¾¾

Bit 7~2

Unimplemented, read as

²0²

Bit 1~0

TMnAH: TMn CCRA High Byte Register bit 1 ~ bit 0

TMn 10-bit CCRA bit 9 ~ bit 8

· TMnC0 Register

Bit

76543210

Name

TnPAU

TnCK2

TnCK1

TnCK0

TnON

TnRP2

TnRP1

TnRP0

R/W

POR

00000000

Bit 7

TnPAU: TMn Counter Pause Control

0: run

1: pause

The counter can be paused by setting this bit high. Clearing the bit to zero restores normal

counter operation. When in a Pause condition the TM will remain powered up and continue to

consume power. The counter will retain its residual value when this bit changes from low to high

and resume counting from this value when the bit changes to a low value again.

Bit 6~4

TnCK2~TnCK0: Select TM0 Counter clock

000: fSYS/4

001: fSYS

010: fH/16

011: fH/64

100: fTBC

101: underined

110: TCKn rising edge clock

111: TCKn falling edge clock

These three bits are used to select the clock source for the TM. Selecting the Reserved clock

input will effectively disable the internal counter. The external pin clock source can be chosen to

be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and

fTBC are other internal clocks, the details of which can be found in the oscillator section.

Bit 3

TnON: TMn Counter On/Off Control

0: Off

1: On

This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to

run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting

and turn off the TM which will reduce its power consumption. When the bit changes state from

low to high the internal counter value will be reset to zero, however when the bit changes from

high to low, the internal counter will retain its residual value.

If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial

condition, as specified by the TnOC bit, when the TnON bit changes from low to high.

Bit 2~0

TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TM0 Counter bit 9~bit 7

Comparator P Match Period

000: 1024 TMn clocks

001: 128 TMn clocks

010: 256 TMn clocks

011: 384 TMn clocks

100: 512 TMn clocks

101: 640 TMn clocks

110: 768 TMn clocks

111: 896 TMn clocks

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