SM5K3 datasheet(17/28 Pages) SHARP

17 / 28 page

SM5K3/SM5K4/SM5K5

- 17 -

• IME flag (master enable flag)

The IME enables or disables all interrupts at the

same time. The IE command, when executed, sets

the IME flag and enables the interrupt specified by

the mask flag setting. The ID command resets the

IME flag, disabling process of any interrupt request.

Setting the IME flag to reset after releasing

hardware reset, all interrupts are inhibited.

• Mode register RE (interrupt mask flag)

The mode register RE (RE0, RE1 and RE2;

interrupt mask flag) individually enables or disables

three type of interrupts.

Timer/Counter

The SM5K3/5K4/5K5 have a pair of built-in

timer/counter. The timer/counter are used to handle

periodic interrupts and to count. The overflowing

timer can be used to disable the halt mode. The

timer/counter serve as interval timer.

The timer/counter consists of an 8-bit count register

RA, modulo register RB (for counter initial value

setting), 15-bit divider and 4-bit mode register RC

(for count clock selection). The configuration of the

timer/counter is shown in Fig. 10.

fSYS

System clock

P11 pin

( external event clock )

Divider

Mode register

( RC register )

fSYS / 2

03 03

fSYS / 2

I FT

Modulo register

( RB register )

Count register

( RA register )

After setting BL = 0BH

OUT command ( RB

←[ X, A ] )

IN command ( [ X, A ]

←RB )

After setting BL = 0AH

OUT command

After setting BL = 0AH

IN command

Interrupt request flag

Fig. 10

Configuration of Timer/Counter

• Selecting count clock

A count clock is selected by the bit settings in the

mode register RC.

LOWER 2-BIT OF RC BITS

SELECTED COUNT CLOCK

fSYS (system clock)

fSYS/27

fSYS/215

External event clock (P11)

Table 5

Count Clock Selection

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