LPC1786 datasheet(83/117 Pages) NXP

83 / 117 page

LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

83 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 17. External static memory read/write access (PB =1)

RD1

WR1

WR8

WR4

WR8

RD2

RD7

RD4

BLSx

RD5

WR6

WR2

RD5

RD6

RD3

EOR

EOW

WR3

WR5

WR7

002aag215

Fig 18. External static memory burst read cycle

RD5

BLSx

002aag216

Table 16.

Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00

CL =30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. All programmable delays EMCDLYCTL are bypassed.

Values guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Common to read and write cycles

td(SV)

chip select valid delay time

2.9

4.2

6.2

th(S)

chip select hold time

1.2

1.8

3.3

td(RASV)

row address strobe valid delay time

2.8

4.2

6.2

th(RAS)

row address strobe hold time

1.3

1.9

3.5

td(CASV)

column address strobe valid delay time

2.8

4.2

6.2

th(CAS)

column address strobe hold time

1.3

1.9

3.5

td(WV)

write valid delay time

3.6

5.2

7.7

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