LPC1786 datasheet(67/117 Pages) NXP

67 / 117 page

LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

67 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Section 7.33.3), causing reset to remain asserted until the external Reset is de-asserted,

the oscillator is running, a fixed number of clocks have passed, and the flash controller

has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

7.34.2 Brownout detection

The LPC178x/7x include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this

voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt

Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the

NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading

a dedicated status register.

The second stage of low-voltage detection asserts reset to inactivate the LPC178x/7x

when the voltage on the VDD(REG)(3V3) pins falls below 2.65 V. This reset prevents

alteration of the flash as operation of the various elements of the chip would otherwise

become unreliable due to low voltage. The BOD circuit maintains this reset down below

1 V, at which point the power-on reset circuitry maintains the overall reset.

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event

loop to sense the condition.

7.34.3 Code security (Code Read Protection - CRP)

This feature of the LPC178x/7x allows user to enable different levels of security in the

system so that access to the on-chip flash and use of the JTAG and ISP can be restricted.

When needed, CRP is invoked by programming a specific pattern into a dedicated flash

location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and flash field updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full flash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.

It is up to the user’s application to provide (if needed) flash update mechanism using IAP

calls or call reinvoke ISP command to enable flash update via UART0.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

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