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TMS570LS3137 bảng dữ liệu(PDF) 144 Page - Texas Instruments

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TMS570LS3137 bảng dữ liệu(HTML) 144 Page - Texas Instruments

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TMS570LS3137
SPNS162.
– SEPTEMBER 2011
www.ti.com
5.10.4 MibSPI/SPI Master Mode I/O Timing Specifications
Table 5-23. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO.
Parameter
MIN
MAX
Unit
1
tc(SPC)M
Cycle time, SPICLK(4)
40
256tc(VCLK)
ns
2(5)
tw(SPCH)M
Pulse duration, SPICLK high (clock
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
ns
polarity = 0)
tw(SPCL)M
Pulse duration, SPICLK low (clock
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
polarity = 1)
3(5)
tw(SPCL)M
Pulse duration, SPICLK low (clock
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
ns
polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high (clock
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
polarity = 1)
4(5)
td(SPCH-SIMO)M
Delay time, SPISIMO valid before
0.5tc(SPC)M – 5
ns
SPICLK low (clock polarity = 0)
td(SPCL-SIMO)M
Delay time, SPISIMO valid before
0.5tc(SPC)M – 5
SPICLK high (clock polarity = 1)
5(5)
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
0.5tc(SPC)M – tf(SPC) – 3
ns
SPICLK low (clock polarity = 0)
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
0.5tc(SPC)M – tr(SPC) – 3
SPICLK high (clock polarity = 1)
6(5)
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK
0.5tf(SPC) + 2
ns
low (clock polarity = 0)
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK
0.5tf(SPC) + 2
high (clock polarity = 1)
7(5)
th(SPCL-SOMI)M
Hold time, SPISOMI data valid after
5
ns
SPICLK low (clock polarity = 0)
th(SPCH-SOMI)M
Hold time, SPISOMI data valid after
5
SPICLK high (clock polarity = 1)
8(6)
tC2TDELAY
Setup time CS active
CSHOLD = 0
C2TDELAY*tc(VCLK) + 2*tc(VCLK)
(C2TDELAY+2) * tc(VCLK) -
ns
until SPICLK high
- tf(SPICS) + tr(SPC) – 15
tf(SPICS) + tr(SPC) + 3
(clock polarity = 0)
CSHOLD = 1
C2TDELAY*tc(VCLK) + 3*tc(VCLK)
(C2TDELAY+3) * tc(VCLK) -
- tf(SPICS) + tr(SPC) – 15
tf(SPICS) + tr(SPC) + 3
Setup time CS active
CSHOLD = 0
C2TDELAY*tc(VCLK) + 2*tc(VCLK)
(C2TDELAY+2) * tc(VCLK) -
ns
until SPICLK low
- tf(SPICS) + tf(SPC) – 15
tf(SPICS) + tf(SPC) + 3
(clock polarity = 1)
CSHOLD = 1
C2TDELAY*tc(VCLK) + 3*tc(VCLK)
(C2TDELAY+3) * tc(VCLK) -
- tf(SPICS) + tf(SPC) – 15
tf(SPICS) + tf(SPC) + 3
9(6)
tT2CDELAY
Hold time SPICLK low CS until inactive
0.5*tc(SPC)M +
0.5*tc(SPC)M +
ns
(clock polarity = 0)
T2CDELAY*tc(VCLK) + tc(VCLK) -
T2CDELAY*tc(VCLK) + tc(VCLK) -
tf(SPC) + tr(SPICS) - 5
tf(SPC) + tr(SPICS) + 8
Hold time SPICLK high until CS
0.5*tc(SPC)M +
0.5*tc(SPC)M +
ns
inactive (clock polarity = 1)
T2CDELAY*tc(VCLK) + tc(VCLK) -
T2CDELAY*tc(VCLK) + tc(VCLK) -
tr(SPC) + tr(SPICS) - 5
tr(SPC) + tr(SPICS) + 8
10
tSPIENA
SPIENAn Sample point
(C2TDELAY+1) * tc(VCLK) -
(C2TDELAY+1)*tc(VCLK)
ns
tf(SPICS) – 25
11
tSPIENAW
SPIENAn Sample point from write to
(C2TDELAY+2)*tc(VCLK)
ns
buffer
(1)
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2)
tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3)
For rise and fall timings, see the
"switching characteristics for output timings versus load capacitance" table.
(4)
When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6)
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
144
Peripheral Information and Electrical Specifications
Copyright
© 2011, Texas Instruments Incorporated
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