TMS570LS3137 datasheet(64/159 Pages) TI

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TMS570LS3137

SPNS162.

– SEPTEMBER 2011

www.ti.com

Table 4-13. Clock Domain Descriptions (continued)

Clock Domain Name

Default Clock

Clock Source

Description

Source

Selection Register

VCLKA3_DIVR

VCLK

VCLKACON1

•

Divided down from the AVCLK3_S using the VCLKA3R field of

the VCLKACON1 register at address 0xFFFFE140

•

Frequency can be VCLKA3_S/1, VCLKA3_S/2, ..., or

VCLKA3_S/8

•

Default frequency is VCLKA3_S/2

•

Is disabled separately via the VCLKACON1 register

VCLKA3_DIV_CDDIS bit only if the VCLKA3_S clock is not

disabled

VCLKA4

VCLK

VCLKACON1

•

Defaults to VCLK as the source

•

Is disabled via the CDDISx registers bit 11

RTICLK

VCLK

RCLKSRC

•

Defaults to VCLK as the source

•

If a clock source other than VCLK is selected for RTICLK, then

the RTICLK frequency must be less than or equal to VCLK/3

–

Application can ensure this by programming the RTI1DIV

field of the RCLKSRC register, if necessary

•

Is disabled via the CDDISx registers bit 6

System Information and Electrical Specifications

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