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TMS570LS3137 bảng dữ liệu(PDF) 58 Page - Texas Instruments

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TMS570LS3137 bảng dữ liệu(HTML) 58 Page - Texas Instruments

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TMS570LS3137
SPNS162.
– SEPTEMBER 2011
www.ti.com
4.5.6.1
Application Sequence for CPU Self-Test
1. Configure clock domain frequencies.
2. Select number of test intervals to be run.
3. Configure the timeout period for the self-test run.
4. Enable self-test.
5. Wait for CPU reset.
6. In the reset handler, read CPU self-test status to identify any failures.
7. Retrieve CPU state if required.
For more information see the TMS570LS31X/21X Technical Reference Manual (SPNU499).
4.5.6.2
CPU Self-Test Clock Configuration
The maximum clock rate for the self-test is 90MHz. The STCCLK is divided down from the CPU clock.
This divider is configured by the STCCLKDIV register at address 0xFFFFE108.
For more information see the TMS570LS31X/21X Technical Reference Manual (SPNU499).
4.5.6.3
CPU Self-Test Coverage
Table 4-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test
cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.
Table 4-7. CPU Self-Test Coverage
INTERVALS
TEST COVERAGE, %
TEST CYCLES
0
0
0
1
62.13
1365
2
70.09
2730
3
74.49
4095
4
77.28
5460
5
79.28
6825
6
80.90
8190
7
82.02
9555
8
83.10
10920
9
84.08
12285
10
84.87
13650
11
85.59
15015
12
86.11
16380
13
86.67
17745
14
87.16
19110
15
87.61
20475
16
87.98
21840
17
88.38
23205
18
88.69
24570
19
88.98
25935
20
89.28
27300
21
89.50
28665
22
89.76
30030
23
90.01
31395
24
90.21
32760
58
System Information and Electrical Specifications
Copyright
© 2011, Texas Instruments Incorporated
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