TMS570LS3137 datasheet(138/159 Pages) TI

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SDA

SCL

w(SDAH)

w(SCLL)

w(SCLH)

w(SP)

h(SCLL-SDAL)

h(SDA-SCLL)

h(SCLL-SDAL)

su(SCLH-SDAL)

f(SCL)

c(SCL)

r(SCL)

su(SCLH-SDAH)

Stop

Start

Repeated Start

Stop

su(SDA-SCLH)

TMS570LS3137

SPNS162.

– SEPTEMBER 2011

www.ti.com

5.9.2

I2C I/O Timing Specifications

Table 5-18. I2C Signals (SDA and SCL) Switching Characteristics(1)

Parameter

Standard Mode

Fast Mode

Unit

MIN

MAX

MIN

MAX

tc(I2CCLK)

Cycle time, Internal Module clock for I2C,

75.2

149

75.2

149

prescaled from VCLK

tc(SCL)

Cycle time, SCL

2.5

tsu(SCLH-SDAL)

Setup time, SCL high before SDA low (for a

4.7

0.6

repeated START condition)

th(SCLL-SDAL)

Hold time, SCL low after SDA low (for a repeated

0.6

START condition)

tw(SCLL)

Pulse duration, SCL low

4.7

1.3

tw(SCLH)

Pulse duration, SCL high

0.6

tsu(SDA-SCLH)

Setup time, SDA valid before SCL high

250

100

th(SDA-SCLL)

Hold time, SDA valid after SCL low (for I2C bus

3.45(2)

0.9

devices)

tw(SDAH)

Pulse duration, SDA high between STOP and

4.7

1.3

START conditions

tsu(SCLH-SDAH)

Setup time, SCL high before SDA high (for STOP

4.0

0.6

condition)

tw(SP)

Pulse duration, spike (must be suppressed)

(3)

Capacitive load for each bus line

400

(1)

The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2)

The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL

signal.

(3)

Cb = The total capacitance of one bus line in pF.

Figure 5-9. I2C Timings

138

Peripheral Information and Electrical Specifications

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