TMS570LS3137 datasheet(118/159 Pages) TI

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TMS570LS3137

SPNS162.

– SEPTEMBER 2011

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Table 5-4. Alternate MIBADC1 Event Trigger Hookup (continued)

Event #

Source Select Bits for G1, G2 or Event

Trigger

(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])

010

N2HET1[27]

011

RTI compare 0 interrupt

100

N2HET1[17]

101

N2HET1[19]

110

N2HET1[11]

111

N2HET2[13]

The selection between the default MIBADC1 event trigger hook-up versus the alternate event trigger

hook-up is done by multiplexing control module register 30 bits 0 and 1.

If 30[0] = 1, then the default MibADC1 event trigger hook-up is used.

If 30[0] = 0 and 30[1] = 1, then the alternate MibADC1 event trigger hook-up is used.

NOTE

For ADEVT trigger source, the connection to the MibADC1 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

configuring ADEVT as an output function on to the pad (via the mux control), or by driving

the ADEVT signal from an external trigger source as input. If the mux control module is used

to select different functionality instead of the ADEVT signal, then care must be taken to

disable ADEVT from triggering conversions; there is no multiplexing on the input connection.

NOTE

For N2HETx trigger sources, the connection to the MibADC1 module trigger input is made

from the input side of the output buffer (at the N2HETx module boundary). This way, a

trigger condition can be generated even if the N2HETx signal is not selected to be output on

the pad.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

5.2.2.3

Default MIBADC2 Event Trigger Hookup

Table 5-5. MIBADC2 Event Trigger Hookup

Event #

Source Select Bits for G1, G2 or Event

Trigger

(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])

000

AD2EVT

001

N2HET1[8]

010

N2HET1[10]

011

RTI compare 0

100

N2HET1[12]

101

N2HET1[14]

110

GIOB[0]

111

GIOB[1]

118

Peripheral Information and Electrical Specifications

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