TMS320LC2401AVFS datasheet(86/88 Pages) TI

86 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

peripheral register description (continued)

Table 16. Lx2401A DSP Peripheral Register Description (Continued)

ADDR

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

REG

ADDR

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS (CONTINUED)

0742Fh

—

T1OFINT

FLAG

T1UFINT

FLAG

T1CINT

FLAG

EVAIFRA

0742Fh

T1PINT

FLAG

—

CMP3INT

FLAG

CMP2INT

FLAG

CMP1INT

FLAG

PDPINTA

FLAG

EVAIFRA

—

07430h

—

T2OFINT

FLAG

T2UFINT

FLAG

T2CINT

FLAG

T2PINT

FLAG

EVAIFRB

—

07431h

—

CAP3INT

FLAG

CAP2INT

FLAG

CAP1INT

FLAG

EVAIFRC

07432h

074FFh

Illegal

07500h

0753Fh

Reserved

I/O MEMORY SPACE

0FF0Fh

—

FCMR

0FF0Fh

—

FCMR

WAIT-STATE GENERATOR CONTROL REGISTER

0FFFFh

—

BVIS.1

BVIS.0

ISWS.2

WSGR

0FFFFh

ISWS.1

ISWS.0

DSWS.2

DSWS.1

DSWS.0

PSWS.2

PSWS.1

PSWS.0

WSGR

These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-

sponding pins have not been bonded out of the device.

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