TMS320LC2401AVFS datasheet(73/88 Pages) TI

73 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

interrupt timing

INT refers to XINT1, XINT2, and PDPINTA.

switching characteristics over recommended operating conditions (see Figure 36)

PARAMETER

MIN

MAX

UNIT

td(PDP-PWM)HZ

Delay time, PDPINTA low to PWM

if bit 6 of SCSR2 = 0

(6 + 1)tc(CO) + 12†

td(PDP-PWM)HZ

Delay time, PDPINTA low to PWM

high-impedance state

if bit 6 of SCSR2 = 1

(12+ 1)tc(CO) + 12†

td(INT)

Delay time, INT low/high to interrupt-vector

fetch

10tc(CO)+tw(INT)

† Includes i/p qualifier cycles plus synchronization plus propagation delay

timing requirements (see Figure 36)

MIN

MAX

UNIT

tw(INT)

Pulse duration, INT input low/high

if bit 6 of SCSR2 = 0

6tc(CO)

tw(INT)

Pulse duration, INT input low/high

if bit 6 of SCSR2 = 1

12tc(CO)

tw(PDP)

Pulse duration, PDPINTA input low

if bit 6 of SCSR2 = 0

6tc(CO)

tw(PDP)

Pulse duration, PDPINTA input low

if bit 6 of SCSR2 = 1

12tc(CO)

PWM†

PDPINTA

CLKOUT

tw(PDP)

td(PDP-PWM)HZ

XINT1, XINT2

tw(INT)

Interrupt Vector

td(INT)

† PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTA is taken

high depends on the state of the FCOMPOE bit.

A0−A15

(Internal Bus)

Figure 36. External Interrupts Timing

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