TMS320F2812 datasheet(137/170 Pages) TI

137 / 170 page

Lead 1

Active

Trail

XCLKOUT = XTIMCLK

XCLKOUT = 1/2 XTIMCLK

XA[0:18]

XD[0:15]

XREADY(Synch)

d(XCOHL-XWEL)

d(XCOHL-XWEH)

d(XCOHL-XZCSH)

d(XCOH-XA)

WS (Synch)

XZCS0AND1 XZCS2

XZCS6AND7

XRD

XWE

XR/W

d(XCOH-XZCSL)

d(XCOH-XRNWL)

d(XCOHL-XRNWH)

en(XD)XWEL

h(XD)XWEH

su(XRDHsynchH)XCOHL

su(XRDYsynchL)XCOHL

DOUT

d(XWEL-XD)

dis(XD)XRNW

h(XRDYsynchL)

h(XRDYsynchH)XZCSH

See Note (E)

See Note (D)

See

Notes (A)

and (B)

See Note (C)

= Don’t care. Signal can be high or low during this time.

Legend:

e(XRDYsynchH)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S – APRIL 2001 – REVISED MARCH 2011

All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an

alignment cycle before an access to meet this requirement.

During alignment cycles, all signals will transition to their inactive state.

During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes

alignment cycles.

For each sample, setup time from the beginning of the access can be calculated as:

D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL

where n is the sample number (n = 1, 2, 3 and so forth).

Reference for the first sample is with respect to this point

E = (XWRLEAD + XWRACTIVE) tc(XTIM)

Figure 6-35. Write With Synchronous XREADY Access

XTIMING register parameters used for this example:

XRDLEAD

XRDACTIVE

XRDTRAIL

USEREADY

X2TIMING

XWRLEAD

XWRACTIVE

XWRTRAIL

READYMODE

0 = XREADY

N/A(1)

≥ 1

(Synch)

(1)

N/A = “Don’t care” for this example

Electrical Specifications

137

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