TMS320F2812 datasheet(35/170 Pages) TI

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TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S – APRIL 2001 – REVISED MARCH 2011

3.2.9

L0, L1, H0 SARAMs

The F281x and C281x contain an additional 16K x 16 of single-access RAM, divided into three blocks

(4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block

is mapped to both program and data space.

3.2.10 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after

device reset and checks several GPIO pins to determine which boot mode to enter. For example, the user

can select to execute code already present in the internal Flash or download new software to internal

RAM through one of several serial ports. Other boot modes exist as well. The Boot ROM also contains

standard tables, such as SIN/COS waveforms, for use in math-related algorithms. Table 3-4 shows the

details of how various boot modes may be invoked. See the TMS320x281x DSP Boot ROM Reference

Guide (literature number SPRU095), for more information.

Table 3-4. Boot Mode Selection(1)(2)

GPIOF4

GPIOF12

GPIOF3

GPIOF2

BOOT MODE SELECTED

(SCITXDA)

(MDXA)

(SPISTEA)

(SPICLK)

GPIO PU status(3)

No PU

Jump to Flash/ROM address 0x3F 7FF6.

A branch instruction must have been programmed here prior to

reset to re-direct code execution as desired.

Call SPI_Boot to load from an external serial SPI EEPROM

Call SCI_Boot to load from SCI-A

Jump to H0 SARAM address 0x3F 8000

Jump to OTP address 0x3D 7800

Call Parallel_Boot to load from GPIO Port B

(1)

Extra care must be taken due to any effect toggling SPICLK to select a boot mode may have on external logic.

(2)

If the boot mode selected is Flash, H0, or OTP, then no external code is loaded by the bootloader.

(3)

PU = pin has an internal pullup. No PU = pin does not have an internal pullup.

3.2.11 Security

The F281x and C281x support high levels of security to protect the user firmware from being

reverse-engineered. The security features a 128-bit password (hardcoded for 16 wait states), which the

user programs into the flash. One code security module (CSM) is used to protect the flash/ROM/OTP and

the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory

contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable

software that would export the secure memory contents. To enable access to the secure blocks, the user

must write the correct 128-bit ”KEY” value, which matches the value stored in the password locations

within the Flash/ROM.

NOTE

•

When the code-security passwords are programmed, all addresses between 0x3F 7F80

and 0x3F 7FF5 cannot be used as program code or data. These locations must be

programmed to 0x0000.

•

If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may

be used for code or data.

•

On ROM devices, addresses 0x3F 7FF2–0x3F 7FF5 and 0x3D 7BFC–0x3D 7BFF are

reserved for TI, irrespective of whether code security has been used or not. User

application should not use these locations in any way.

•

The 128-bit password (at 0x3F 7FF8–0x3F 7FFF) must not be programmed to zeros.

Doing so would permanently lock the device.

Functional Overview

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