TMS320F2812 datasheet(38/170 Pages) TI

38 / 170 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S – APRIL 2001 – REVISED MARCH 2011

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3.2.19 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This multiplexing

enables use of a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are

configured as inputs. The user can then individually program each pin for GPIO mode or peripheral signal

mode. For specific inputs, the user can also select the number of input qualification cycles to filter

unwanted noise glitches.

3.2.20 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock

prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter

reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.

When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is

reserved for the DSP/BIOS Real-Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is not

being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be

connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.

3.2.21 Control Peripherals

The F281x and C281x support the following peripherals that are used for embedded control and

communication:

EV:

The event manager module includes general-purpose timers, full-compare/PWM units,

capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event

managers are provided which enable two three-phase motors to be driven or four

two-phase motors. The event managers on the F281x and C281x are compatible to the

event managers on the 240x devices (with some minor enhancements).

ADC:

The ADC block is a 12-bit converter, single ended, 16-channels. It contains two

sample-and-hold units for simultaneous sampling.

3.2.22 Serial Port Peripherals

The F281x and C281x support the following serial communication peripherals:

eCAN:

This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time

stamping of messages, and is CAN 2.0B-compliant.

McBSP:

The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality

codecs for modem applications or high-quality stereo audio DAC devices. The McBSP

receive and transmit registers are supported by a 16-level FIFO that significantly reduces

the overhead for servicing this peripheral.

SPI:

The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (one to sixteen bits) to be shifted into and out of the device at a

programmable bit-transfer rate. Normally, the SPI is used for communications between

the DSP controller and external peripherals or another processor. Typical applications

include external I/O or peripheral expansion through devices such as shift registers,

display drivers, and ADCs. Multi-device communications are supported by the

master/slave operation of the SPI. On the F281x and C281x, the port supports a

16-level, receive-and-transmit FIFO for reducing servicing overhead.

SCI:

The serial communications interface is a two-wire asynchronous serial port, commonly

known as UART. On the F281x and C281x, the port supports a 16-level,

receive-and-transmit FIFO for reducing servicing overhead.

Functional Overview

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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

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