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PCF8531U2DA bảng dữ liệu(PDF) 31 Page - NXP Semiconductors |
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PCF8531U2DA bảng dữ liệu(HTML) 31 Page - NXP Semiconductors |
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31 / 51 page ![]() PCF8531 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 — 16 May 2011 31 of 51 NXP Semiconductors PCF8531 34 x 128 pixel matrix driver 10.3 Command decoder The command decoder identifies command words that arrive on the I2C-bus. The most significant bit of a control byte is the continuation bit Co. If this bit is logic 1, it indicates that only one data byte (either command or RAM data) will follow. If this bit is logic 0, it indicates that a series of data bytes (either command or RAM data) may follow. The DB6 bit of a control byte is the RAM data/command bit RS. When this bit is logic 1, it indicates that another RAM data byte will be transferred next. If the bit is logic 0, it indicates that another command byte will be transferred next. • Pairs of bytes; information in the second byte, the first byte determines whether information is display or instruction data • Stream of information bytes after Co = 0; display or instruction data, depending on last RS. Fig 18. Slave address and control byte mgs474 S 011110 SA0 A slave address R/W Co RS XXXXXX control byte Fig 19. Master transmits to slave receiver; write mode mgs475 S 0 11110 S A 0 0A acknowledge from PCF8531 acknowledge from PCF8531 acknowledge from PCF8531 acknowledge from PCF8531 acknowledge from PCF8531 1 control byte A data byte data byte n ≥ 0 bytes 1 byte slave address MSB . . . . . . . . . . . LSB 2n ≥ 0 bytes A Co Co 0A A P RS R/W control byte RS |
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