MPC5673K datasheet(107/140 Pages) FREESCALE

107 / 140 page

Electrical characteristics

MPC5675K Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

107

3.21.4

Reset sequence—start condition

The impact of the voltage thresholds on the starting point of the internal reset sequence are becoming

important if the voltage rails / signals ramp up with a very slow slew rate compared to the overall reset

sequence duration.

3.21.4.1

Internal VREG mode

Figure 26 shows the voltage threshold that determines the start of the Destructive Reset Sequence, BIST

enabled and the start for the Destructive Reset Sequence, BIST disabled. The last voltage rail crossing the

levels shown in Figure 26 determines the start of the reset times specified in Table 58.

Figure 26. Reset sequence start in internal VREG mode

3.21.4.2

External VREG mode

Figure 27 and Figure 28 show the voltage thresholds that determine the start of the Destructive Reset

Sequence, BIST enabled and the start for the Destructive Reset Sequence, BIST disabled.

NOTE

RESET_SUP must not be released unless VDD_LV_xxx is within its valid

range of operation.

7 If RESET is configured for long reset (default) and if BIST is disabled via device configuration data stored in the

shadow sector of the NVM.

8 If RESET is configured for short reset.

9 Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for the functional

reset source which triggered the reset sequence.

Table 60. Voltage thresholds

Variable name

Value

Vmin

LvdReg – 3.5%

Vmax

LvdReg + 3.5%

Supply Rail

VDD_HV_PMU

VDD_HV_IO

VDD_HV_FLASH

VDD_HV_ADV

Vmax

Supply Rail

Vmin

TReset, min starts here

TReset, max starts here

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