PCIMX536AVV8C datasheet(38/178 Pages) FREESCALE

38 / 178 page

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2

Freescale Semiconductor

Electrical Characteristics

4.4.3

UHVIO Output Buffer Impedance

Table 19 shows the UHVIO output buffer impedance.

4.4.4

LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

4.5

I/O AC Parameters

This section includes the AC parameters of the following I/O types:

•

General Purpose I/O (GPIO)

•

Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes

•

Low Voltage I/O (LVIO)

•

Ultra High Voltage I/O (UHVIO)

•LVDS I/O

The load circuit and output transition time waveforms are shown in Figure 5 and Figure 6.

Figure 5. Load Circuit for Output

Figure 6. Output Transition Time Waveform

Table 19. UHVIO Output Buffer Impedance

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

OVDD

1.95 V

OVDD

3.0 V

OVDD

1.875 V

OVDD

3.3 V

OVDD

1.65 V

OVDD

3.6 V

Output Driver

Impedance

Rpu

Low Drive Strength, Ztl = 150

Medium Drive Strength, Ztl = 75

High Drive Strength, Ztl = 50

114

124

135

198

206

103

Output Driver

Impedance

Rpd

Low Drive Strength, Ztl = 150

Medium Drive Strength, Ztl = 75

High Drive Strength, Ztl = 50

118

126

154

179

217

109

Test Point

From Output

Under Test

CL includes package, probe and fixture capacitance

OVDD

20%

80%

20%

Output (at pad)

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