PCIMX536AVV8C datasheet(3/178 Pages) FREESCALE

3 / 178 page

Introduction

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2

Freescale Semiconductor

1.1

Ordering Information

Table 1 provides ordering information.

1.2

Features

The i.MX53xA multimedia applications processor (AP) is based on the ARM Platform, which has the

following features:

•

MMU, L1 instruction and L1 data cache

•

Unified L2 cache

•

Target frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz

•

Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)

coprocessor supporting VFPv3

•

TrustZone

The memory system consists of the following components:

•

Level 1 cache:

— Instruction (32 Kbyte)

— Data (32 Kbyte)

•

Level 2 cache:

— Unified instruction and data (256 Kbyte)

•

Level 2 (internal) memory:

— Boot ROM, including HAB (64 Kbyte)

— Internal multimedia/shared, fast access RAM (128 Kbyte)

— Secure/non-secure RAM (16 Kbyte)

•

External memory interfaces:

— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte

— 32-bit LPDDR2

— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC

— 8/16-bit NOR Flash, PSRAM, and cellular RAM.

Table 1. Ordering Information

Part Number1

1 Part numbers with a PC prefix indicate non production engineering parts.

Mask Set

Features

Notes

Package2

2 Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.

MCIMX536AVV8C

N78C

800 MHz, full feature set

—

19 x 19 mm, 0.8 mm pitch BGA

Case TEPBGA-2

PCIMX536AVV8C

N78C

800 MHz, full feature set

—

19 x 19 mm, 0.8 mm pitch BGA

Case TEPBGA-2

MCIMX534AVV8C

N78C

800 MHz, no hardware video

codecs

—

19 x 19 mm, 0.8 mm pitch BGA

Case TEPBGA-2

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