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PIC16F1847 bảng dữ liệu(PDF) 207 Page - Microchip Technology |
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PIC16F1847 bảng dữ liệu(HTML) 207 Page - Microchip Technology |
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207 / 408 page  2011 Microchip Technology Inc. Preliminary DS41453B-page 207 PIC16(L)F1847 24.1.5 CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 24.1.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the Alternate Pin Func- tion registers, APFCON0 and APFCON1. To determine which pins can be moved and what their default loca- tions are upon a Reset, see Section 12.1 “Alternate Pin Function” for more information. TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL 120 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 228 CCPR1L Capture/Compare/PWM Register Low Byte (LSB) 206* CCPR1H Capture/Compare/PWM Register High Byte (MSB) 206* CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 172 CM1CON1 C1INTP C1INTN C1PCH<1:0> — — C1NCH<1:0> 173 CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 173 CM2CON1 C2INTP C2INTN C2PCH<1:0> — — C2NCH<1:0> 173 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 228 CCPR2L Capture/Compare/PWM Register Low Byte (LSB) 228 CCPR2H Capture/Compare/PWM Register High Byte (MSB) 228 CCP3CON — — DC3B<1:0> CCP3M<3:0> 228 CCPR3L Capture/Compare/PWM Register Low Byte (LSB) 228 CCPR3H Capture/Compare/PWM Register High Byte (MSB) 228 CCP4CON — — DC4B<1:0> CCP4M<3:0)> 228 CCPR4L Capture/Compare/PWM Register Low Byte (LSB) 228 CCPR4H Capture/Compare/PWM Register High Byte (MSB) 228 INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 89 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 90 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 91 PIE3 — — CCP4IE CCP3IE TMR6IE —TMR4IE — 92 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 94 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF 95 PIR3 — — CCP4IF CCP3IF TMR6IF —TMR4IF — 96 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC —TMR1ON 187 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 188 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 179* TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 179* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Capture mode. * Page provides register information. |
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