R5F52107ADFN datasheet(51/92 Pages) RENESAS

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R01DS0041EJ0050 Rev.0.50

Page 51 of 90

Apr 15, 2011

RX210 Group

2. CPU

Under development Preliminary document

Specifications in this document are tentative and subject to change.

2.8.2.2

Instructions Converted into Multiple Micro-Operations and Pipeline Processing

The table below lists the instructions that are converted into multiple micro-operations. The number of cycles in the table

indicates the number of cycles during no-wait memory access.

Table 2.14

Instructions that are Converted into Multiple Micro-Operations (1 / 2)

Instruction

Mnemonic (indicates the common operation when

the size is omitted)

Reference

Figure

Number of Cycles

Arithmetic/logic instructions

(memory source operand)

 {ADC, ADD, AND, CMP, MAX, MIN, MUL, OR, SBB,

SUB, TST, XOR} “[Rs], Rd”/“dsp[Rs], Rd”

Figure 2.13

Arithmetic/logic instructions

(division)

 DIV “[Rs],Rd / dsp[Rs],Rd”

—

5 to 22

 DIVU“[Rs],Rd / dsp[Rs],Rd”

—

4 to 20

Arithmetic/logic instructions

(multiplier: 32 × 32

 64 bits)

(register-register, register-

immediate)

 {EMUL, EMULU} “#IMM, Rd”/“Rs, Rd”

Figure 2.15

Arithmetic/logic instructions

(multiply-and-accumulate

operation)

 RMPA.B

—

6+7×floor(n/4)+4×(n%4)

n: Number of processing

bytes*1

 RMPA.W

—

6+5×floor(n/2)+4×(n%2)

n: Number of processing

words*1

 RMPA.L

—

6+4n

n: Number of processing

longwords*1

Arithmetic/logic instructions (64-

bit signed saturation processing

for the RMPA instruction)

 SATR

—

Data transfer instructions

(memory-memory transfer)

 MOV “[Rs], [Rd]”/“dsp[Rs], [Rd]”/“[Rs], dsp[Rd]”/

“dsp[Rs], [Rd]”

 PUSH “[Rs]”/“dsp[Rs]”

Figure 2.14

Bit manipulation instructions

(memory source operand)

 {BCLR, BNOT, BSET, BTST} “#IMM, [Rd]”/

“#IMM, dsp[Rd]”

 BMCnd “#IMM, [Rd]”/“#IMM, dsp[Rd]”

Figure 2.14

Transfer instructions

(load operation)

 POPC “CR”

—

Throughput: 3

Latency: 4*2

Transfer instructions (save

operation of multiple registers)

 PUSHM “Rs-Rs2”

—

n: Number of registers*3

Transfer instructions (restore

operation of multiple registers)

 POPM “Rs-Rs2”

—

Throughput: n

Latency: n + 1

n: Number of

registers*2,*4

Transfer instructions

(register-register)

 XCHG “Rs, Rd”

Figure 2.16

Transfer instructions

(memory-register)

 XCHG “[Rs], Rd”/“dsp[Rs], Rd”

Figure 2.17

Branch instructions

 RTS

—

 RTSD “#IMM”

—

 RTSD “#IMM, Rd-Rd2”

—

Throughput: n<5?5:1+n

Latency: n<4?5:2+n

n: Number of registers*2

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