PIC12F752 datasheet(71/204 Pages) MICROCHIP

71 / 204 page

 2011 Microchip Technology Inc.

Preliminary

DS41576A-page 71

PIC12F752/HV752

9.0

HARDWARE LIMIT TIMER (HLT)

MODULE

The Hardware Limit Timer (HLT) module is a version of

the Timer2-type modules. In addition to all the Timer2-

type features, the HLT can be reset on rising and falling

events from selected peripheral outputs.

The HLT primary purpose is to act as a timed hardware

limit to be used in conjunction with asynchronous

analog feedback applications. In normal operation, the

analog feedback occurs before the HLT period, thereby

resetting the HLTMR1 for the next period and

preventing the HLT output. When the analog feedback

fails to generate a signal within the expected time, then

the HLT output provides a feedback signal in lieu of the

analog signal at the programmed maximum time.

The HLT module incorporates the following features:

• 8-bit Read-Write Timer Register (HLTMR1)

• 8-bit Read-Write Period register (HLTPR1)

• Software programmable prescaler:

-1:1

-1:4

-1:16

• Software programmable postscaler

- 1:1 to 1:16, inclusive

• Interrupt on HLTMR1 match with HLTPR1

• 8 selectable timer Reset inputs (5 reserved)

• Reset on rising and falling event

Refer to Figure 9-1 for a block diagram of the HLT.

FIGURE 9-1:

HLTMR1 BLOCK DIAGRAM

Comparator

HLTimer1 Output

Sets Flag bit HLTMR1IF

HLTMR1

Reset

Postscaler

Prescaler

HLTPR1

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

H1OUTPS<3:0>

H1CKPS<1:0>

Detect

H1FEREN

H1REREN

H1ERS<2:0>

Detect

CCP1 out

C1OUT

C2OUT

‘0’

000

111

H1ON

(to COG module)

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