PCIMX536AVV8B datasheet(115/180 Pages) FREESCALE

115 / 180 page

Electrical Characteristics

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

115

4.7.13

PATA Timing Parameters

This section describes the timing parameters of the Parallel ATA module which are compliant with

ATA/ATAPI-6 specification.

Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode

has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel ATA

module interface consist of a total of 29 pins. Some pins act on different function in different transfer

mode. There are different requirements of timing relationships among the function pins conform with

ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.

Table 69 and Figure 67 define the AC characteristics of all the PATA interface signals in all data transfer

modes.

Figure 67. PATA Interface Signals Timing Diagram

Table 68. PWM Output Timing Parameter

Ref. No.

Parameter

Min

Max

Unit

System CLK frequency1

1 CL of PWMO = 30 pF

ipg_clk

MHz

Clock high time

12.29

—

Clock low time

9.91

—

Clock fall time

—

0.5

Clock rise time

—

0.5

Output delay time

—

9.37

Output setup time

8.71

—

Table 69. AC Characteristics of All Interface Signals

Parameter

Symbol

Min

Max

Unit

SI1

Rising edge slew rate for any signal on ATA interface1

1 SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal

amplitude with all capacitive loads from 15

–40 pF where all signals have the same capacitive load value.

Srise

—1.25

V/ns

SI2

Falling edge slew rate for any signal on ATA interface1

Sfall

—1.25

V/ns

SI3

Host interface signal capacitance at the host connector

Chost

—20

ATA Interface Signals

SI1

SI2

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