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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PCIMX536AVV8B bảng dữ liệu(PDF) 111 Page - Freescale Semiconductor, Inc |
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PCIMX536AVV8B bảng dữ liệu(HTML) 111 Page - Freescale Semiconductor, Inc |
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111 / 180 page  Electrical Characteristics i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 111 Ground = 0.0 V; Load Capacitance = 60 pF; MediaLB speed = 256/512 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as listed below; unless otherwise noted. Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as listed in Table 64; unless otherwise noted. Table 63. MLB 256/512 Fs Timing Parameters Parameter Symbol Min Typ Max Units Comment MLBCLK operating frequency1 1 The MLB controller can shut off MLBCLK to place MediaLB in a low-power state. fmck 11.264 12.288 24.576 24.6272 25.600 MHz Min: 256*fs at 44.0 kHz Typ: 256*fs at 48.0 kHz Typ: 512*fs at 48.0 kHz Max: 512*fs at 48.1 kHz Max: 512*fs PLL unlocked MLBCLK rise time tmckr —— 3 ns VIL TO VIH MLB fall time tmckf —— 3 ns VIH TO VIL MLBCLK cycle time tmckc — — 81 40 — — ns 256*Fs 512*Fs MLBCLK low time tmckl 31.5 30 37 35.5 — — ns 256*Fs 256*Fs PLL unlocked 14.5 14 17 16.5 — — ns 512*Fs 512*Fs PLL unlocked MLBCLK high time tmckh 31.5 30 38 36.5 — — ns 256*Fs 256*Fs PLL unlocked 14.5 14 17 16.5 — — ns 512*Fs 512*Fs PLL unlocked MLBCLK pulse width variation tmpwv —— 2 ns pp Note2 2 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp) MLBSIG/MLBDAT input valid to MLBCLK falling tdsmcf 1— — ns — MLBSIG/MLBDAT input hold from MLBCLK low tdhmcf 0— — ns — MLBSIG/MLBDAT output high impedance from MLBCLK low tmcfdz 0— tmckl ns — Bus Hold Time tmdzh 4— — ns Note3 3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. |
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