PCIMX536AVV8B datasheet(62/180 Pages) FREESCALE

62 / 180 page

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

Electrical Characteristics

4.6.7

DDR SDRAM Specific Parameters (DDR2/LVDDR2, LPDDR2 and

DDR3)

The DDR2/LVDDR2 interface fully complies with JESD79-2E – DDR2 JEDEC release April, 2008,

supporting DDR2-800 and LVDDR2-800.

The DDR3 interface fully complies with JESD79-3D – DDR3 JEDEC release April 2008 supporting

DDR3-800.

The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800.

MAXD

DTACK MAXIMUM delay from

chip dtack input to its internal

FF + 2 cycles for

synchronization

——

—

WE47

Dtack Active to CSx_B Invalid

MAXCO - MAXCSO +

MAXDTI

MAXCO -

MAXCSO +

MAXDTI

—ns

WE48

CSx_B Invalid to Dtack

invalid

—

1 Parameters WE4... WE21 value see column BCD = 0 in Table 38

2 All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.

3 CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.

4 CS Negation. This bit field determines when CS signal is negated during read/write cycles.

5 t is axi_clk cycle time.

6 BE Assertion. This bit field determines when BE signal is asserted during read cycles.

7 BE Negation. This bit field determines when BE signal is negated during read cycles.

Table 39. EIM Asynchronous Timing Parameters Table (continued)Relative Chip Select

Ref

No.

Parameter

Determination by

Synchronous measured

parameters 12

Min

Max

(If 133 Mhz is

supported by

SOC)

Unit

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