PCIMX536AVV8B datasheet(76/180 Pages) FREESCALE

76 / 180 page

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

Electrical Characteristics

Figure 37. MII Transmit Signal Timing Diagram

4.7.5.3

MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 50 lists MII asynchronous inputs signal timing information. Figure 38 shows MII asynchronous

input timings listed in Table 50.

Figure 38. MII Async Inputs Timing Diagram

4.7.5.4

MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

Table 51 lists MII serial management channel timings. Figure 39 shows MII serial management channel

timings listed in Table 51. The MDC frequency should be equal to or less than 2.5 MHz to be compliant

with the IEEE 802.3 MII specification. However, the FEC can function correctly with a maximum MDC

frequency of 15 MHz.

Table 50. MII Async Inputs Signal Timing

Num

Characteristic 1

1 Test conditions: 25pF on each output signal.

Min

Max

Unit

M92

2 FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

FEC_CRS to FEC_COL minimum pulse width

1.5

—

FEC_TX_CLK period

Table 51. MII Transmit Signal Timing

Characteristics1

Min

Max

Unit

M10

FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)

—

M11

FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)

—

M12

FEC_MDIO (input) to FEC_MDC rising edge setup

—

FEC_TX_CLK (input)

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

FEC_CRS, FEC_COL

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