MNSC140CORE datasheet(51/80 Pages) FREESCALE

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AC Timings

MSC8102 Quad Core Digital Signal Processor, Rev. 12

Freescale Semiconductor

2-21

2.5.12 JTAG Signals

Table 2-23.

JTAG Timing

No.

Characteristics

All frequencies

Unit

Min

Max

700

TCK frequency of operation (1/(T

C ×

3); maximum 22 MHz)

0.0

22.0

MHz

701

TCK cycle time

45.0

—

702

TCK clock pulse width measured at VM = 1.6 V

21.0

—

703

TCK rise and fall times

0.0

3.0

704

Boundary scan input data set-up time

5.0

—

705

Boundary scan input data hold time

24.0

—

706

TCK low to output data valid

0.0

40.0

707

TCK low to output high impedance

0.0

40.0

708

TMS, TDI data set-up time

5.0

—

709

TMS, TDI data hold time

25.0

—

710

TCK low to TDO data valid

0.0

44.0

711

TCK low to TDO high impedance

0.0

20.0

712

TRST assert time

100.0

—

713

TRST set-up time to TCK low

40.0

—

Note:

All timings apply to OnCE module data transfers as the OnCE module uses the JTAG port as an interface.

Figure 2-20.

Test Clock Input Timing Diagram

TCK

(Input)

VIH

VIL

701

702

703

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