MNSC140CORE datasheet(22/80 Pages) FREESCALE

22 / 80 page

MSC8102 Quad Core Digital Signal Processor, Rev. 12

1-12

Freescale Semiconductor

Signals/Connections

1.6 GPIO, TDM, UART, and Timer Signals

The general-purpose input/output (GPIO), time-division multiplexed (TDM), universal asynchronous

receiver/transmitter (UART), and timer signals are grouped together because they use a common set of signal lines.

Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-7

describes the signals in this group.

PSDAMUX

PGPL5

Output

System Bus SDRAM Address Multiplexer

Controls the system bus SDRAM address multiplexer when the MSC8102 is in external master

mode.

System Bus UPM General-Purpose Line 5

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

Table 1-7.

GPIO, TDM, UART, and Timer Signals

Signal Name

Type

Description

GPIO0

CHIP_ID0

Input/Output

Input

General-Purpose Input Output 0

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs.

Chip ID 0

Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal.

GPIO1

TIMER0

CHIP_ID1

Input/Output

Input

General-Purpose Input Output 1

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs.

Timer 0

Each signal is configured as either input to or output from the counter. See the

MSC8102 Reference

for configuration details.

Chip ID 1

Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal.

GPIO2

TIMER1

CHIP_ID2

Input/Output

Input

General-Purpose Input Output 2

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs. For details, refer to the

MSC8102 Reference Manual.

Timer 1

Each signal is configured as either input to or output from the counter. For the configuration of the pin

direction, refer to the

MSC8102 Reference Manual.

Chip ID 2

Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal.

GPIO3

TDM3TSYN

IRQ1

Input/Output

Input

General-Purpose Input Output 3

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs. For details, refer to the

MSC8102 Reference Manual GPIO programming model.

TDM3 Transmit Frame Sync

Transmit frame sync for TDM 3.

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Table 1-6.

Memory Controller Signals (Continued)

Signal Name

Type

Description

MNSC140CORE bảng dữ liệu(PDF) 22 Page - Freescale Semiconductor, Inc

MNSC140CORE bảng dữ liệu(HTML) 22 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

bảng dữ liệu tải về

Link URL